1. Field of the Invention
The present invention relates to a semiconductor device including an element isolation insulating film for isolating an element forming region and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, as an example of a semiconductor device having an element isolation insulating film, a semiconductor device having a solid-state image pickup element has been used. In the following, a conventional semiconductor device will be described, in conjunction with the semiconductor device having the solid-state image pickup element.
FIG. 20 shows a circuit configuration of the solid-state image pickup element having a CMOS (Complementary Metal Oxide Semiconductor) type image sensor. As shown in FIG. 20, the solid-state image pickup element has a unit pixel or a unit cell C arranged in matrix. In addition, in the solid-state image pickup element, each of unit cells C is connected to a vertical shift register VS and a horizontal shift register HS.
Each unit cell C has a photodiode PD, a transfer switch M1, a reset switch M2, an amplifier M3 and a selection switch M4. Photodiode PD attains a function corresponding to a photoelectric conversion and storage portion converting incident light to electric charges and storing the resultant charges. Transfer switch Ml attains a function to transfer the charges to amplifier M3.
Transfer switch M1 is controlled by a signal from vertical shift register VS. Reset switch M2 resets photodiode PD by providing the stored charges to a ground electrode. Amplifier M3 amplifies the magnitude of an electrical signal generated by transferring the charges. When selection switch M4 is selected by the vertical shift register and a horizontal shift register, a source region is electrically connected to a drain region, and selection switch M4 outputs an electrical signal to the outside.
Here, each of transfer switch M1, reset switch M2, amplifier M3 and selection switch M4 is fabricated with a MOS transistor.
FIG. 21 is a top view showing a specific configuration of a region R in FIG. 20, and FIG. 22 is a cross-sectional view along the line XXIIxe2x80x94XXII in FIG. 21.
As shown in FIGS. 21 and 22, on the surface of a P-type semiconductor substrate 102, an element isolation insulating film 103 is formed with LOCOS (LOCal Oxidation of Silicon). Further, on the surface of P-type semiconductor substrate 102, photodiode PD, transfer switch M1 and reset switch M2 are arranged side by side.
Photodiode PD is fabricated by a PN junction of P-type semiconductor substrate 102 with an N-type impurity diffusion region (an N-type active region) 104. In the upper portion of N-type impurity diffusion region 104 (in the vicinity of surface of P-type semiconductor substrate 102), a P-type impurity diffusion region (a P-type active region) 105 is formed. P-type impurity diffusion region 105 is formed to such a depth that a depletion layer of the PN junction of P-type semiconductor substrate 102 with N-type impurity diffusion region 104 will not reach the lower surface of P-type impurity diffusion region 105.
Transfer switch M1 has an N-type source region 104, an N-type drain region (an N-type active region, represented as FD (Floating Diffusion) because it sometimes floats during operation) 106a and a gate electrode layer 108a. N-type source region 104 and N-type drain region 106a are formed in P-type semiconductor substrate 102, spaced apart from each other by a prescribed distance. Gate electrode layer 108a is formed on a gate insulating layer 107 above a portion lying between N-type source region 104 and N-type drain region 106a in P-type semiconductor substrate 102.
Note that N-type impurity diffusion region 104 of photodiode PD and N-type source region 104 of transfer switch M1 represent the same region, and that they are merely called differently, from the viewpoint of each element.
Reset switch M2 has a pair of N-type source/drain regions 106a and a gate electrode layer 108b. The pair of N-type source/drain regions 106a are formed on the surface of semiconductor substrate 102, spaced apart from each other by a prescribed distance. Gate electrode layer 108b is formed on a gate insulating layer (not shown) above a region lying between the pair of N-type source/drain regions 106a. 
Note that N-type drain region 106a of transfer switch M1 and one of N-type source/drain regions 106a of reset switch M2 represent the same region, and that they are merely called differently, from the viewpoint of each element.
As shown in FIG. 22, N-type drain region 106a, which is a floating diffusion region FD of the solid-state image pickup element, is in contact with an end portion of an element isolation insulating film 103. A stress is produced in the end portion of element isolation insulating film 103 due to an action in forming the same. The stress produces an interface level (an interface state) in the end portion in a direction parallel to the main surface of P-type semiconductor substrate 102 of element isolation insulating film 103.
In addition, a depletion layer is formed in the PN junction where N-type drain region 106a and P-type semiconductor substrate 102 are joined. If the depletion layer contains a portion where an interface level of the end portion of element isolation insulating film 103 is present, a leakage current is produced along a lower surface of element isolation insulating film 103. The produced leakage current will lower the performance of the solid-state image pickup element.
A problem caused in the floating diffusion region of the solid-state image pickup element will be described more specifically, with reference to FIGS. 23 and 24. In FIG. 23, only an N-type impurity diffusion region 205 as the floating diffusion region of the solid-state image pickup element and a field oxide film 202 as the element isolation insulating film formed by oxidation of the main surface of a P-type semiconductor substrate 201 are shown.
As shown in FIG. 23, field oxide film 202 is formed to a prescribed height and depth above and under the main surface of P-type semiconductor substrate 201. N-type impurity diffusion region 205 is formed in an element forming region surrounded by field oxide film 202. As shown in FIG. 24, N-type impurity diffusion region 205 is formed by impurity injection to the main surface of P-type semiconductor substrate 201, using field oxide film 202 as a mask.
Therefore, an end portion of field oxide film 202 is in contact with an end portion of N-type impurity diffusion region 205. Accordingly, as shown in FIG. 23, the PN junction formed with P-type semiconductor substrate 201 and N-type impurity diffusion region 205 will contact the end portion of field oxide film 202, that is, what is called a xe2x80x9cbird""s beakxe2x80x9d portion 202a. 
Consequently, a depletion layer 210 formed in the vicinity of the PN junction contains an interface level present portion. Therefore, the leakage current caused by a level at an interface of bird""s beak portion 202a with N-type impurity diffusion region 205 and P-type semiconductor substrate 201 will be produced, resulting in lower performance of the solid-state image pickup element.
An object of the present invention is to provide a semiconductor device, which suppresses an occurrence of a leakage current caused by a portion, undesirably included in a depletion layer, where a level is present in an interface of an element isolation insulating film with a semiconductor substrate, and a manufacturing method of the semiconductor device.
A semiconductor device according to the present invention includes a first impurity diffusion region provided in a semiconductor substrate and including at least one impurity diffusion region having an impurity of a first conductivity type; an element isolation insulating film provided in the first impurity diffusion region and isolating one element forming region from another element forming region; and a second impurity diffusion region provided in the first impurity diffusion region and including at least one impurity diffusion region having an impurity of a second conductivity type. The second conductivity type is opposite to the first conductivity type.
In addition, the semiconductor device according to the present invention has an interface level present portion in which a level is produced in an interface where the element isolation insulating film and the semiconductor substrate are in contact.
Further, a position of an interface between the first impurity diffusion region and the second impurity diffusion region is set such that a depletion layer formed to contain the interface between the first impurity diffusion region and the second impurity diffusion region does not reach the interface level present portion.
With the above configuration, an occurrence of a leakage current caused by the interface level present portion undesirably included in the depletion layer during an operation of the semiconductor device is suppressed.
A manufacturing method of a semiconductor device according to the present invention includes a first step of forming in a semiconductor substrate, a first impurity diffusion region including at least one impurity diffusion region having an impurity of a first conductivity type; a second step of forming in the first impurity diffusion region, an element isolation insulating film isolating one element forming region from another element forming region; and a third step of forming in the first impurity diffusion region, a second impurity diffusion region including at least one impurity diffusion region having an impurity of a second conductivity type. The second conductivity type is opposite to the first conductivity type.
After the first to third steps are finished, an interface level present portion is formed, in which a level is produced in an interface where the element isolation insulating film and the semiconductor substrate are in contact. In addition, a position of an interface between the first impurity diffusion region and the second impurity diffusion region is set such that a depletion layer formed to contain the interface between the first impurity diffusion region and the second impurity diffusion region does not reach the interface level present portion.
According to the above manufacturing method of the semiconductor device, the semiconductor device as described above can be manufactured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.